Miss rate prediction across program inputs and cache configurations

IEEE Transactions on Computers

Volumn 56, Issue 3, 2007, Pages 328-343

  Zhong, Yutao ^a   Dropsho, Steven G ^b   Shen, Xipeng ^c   Studer, Ahren ^d   Ding, Chen ^e  

^a George Mason University   (United States)

^b EPFL   (Switzerland)

^c The College of William and Mary   (United States)

^d CARNEGIE MELLON UNIVERSITY   (United States)

^e University of Rochester   (United States)

Author keywords

Cache memories; Compilers; Modeling techniques; Optimization; Performance analysis and design aids

Indexed keywords

COMPUTER SIMULATION; DATA STRUCTURES; INTEGER PROGRAMMING; OPTIMIZATION; PROGRAM COMPILERS;

CACHE SIZE; PERFORMANCE ANALYSIS; PROGRAM DATA SIZE;

CACHE MEMORY;

EID: 33947360666     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.50     Document Type: Article

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