Media Processing: A New Design Target

IEEE Micro

Volumn 16, Issue 4, 1996, Pages 6-

  Lee, Ruby B ^a   Smith, Michael D ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85008066203     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.1996.526920     Document Type: Article

References (14)

1. T. Kondo et al., “Two-Chip MPEG-2 Video Encoder,” IEEE Micro, Vol. 16, No. 2, Apr. 1996, pp. 51–58.
2. CL480 and CL484 VideoCD Decoder User's Manual, Part Number 92-0484-101, C-Cube Microsystems Inc., Milpitas, Calif., 1996.
3. K. Guttag et al., “A Single-Chip Multiprocessor for Multimedia: The MVP,” IEEE Computer Graphics & Applications, Vol. 12, No. 6, Nov. 1992, pp. 53–64.
4. P. Foley, “The Mpact Media Processor Redefines the Multimedia PC,” Proc. Compcon, IEEE Computer Society Press, Los Alamitos, Calif., 1996, pp. 311–318.
5. S. Rathnam and G. Slavenburg, “An Architectural Overview of the Programmable Multimedia Processor, TM-1,” Proc. Compcon, IEEE CS Press, 1996, pp. 319–326.
6. R. Lee, “Accelerating Multimedia with Enhanced Micro-processors,” IEEE Micro, Vol. 15, No. 2, Apr. 1995, pp. 22–32.
7. L. Kohn and N. Margulis, “Introducing the Intel i860 64-Bit Microprocessor,” IEEE Micro, Vol. 9, No. 4, Aug. 1989, pp. 15–30.
8. K. Diefendorff and M. Allen, “Organization of the Motorola 88110 Superscalar RISC Microprocessor,” IEEE Micro, Vol. 12, No. 2, Apr. 1992, pp. 40–63.
9. C. Dowdell and L. Thayer, “Scalable Graphics Enhancements for PA-RISC Workstations,” Proc. Compcon, IEEE CS Press, 1992, pp. 122–128.
10. L. Gwennap, “New PA-RISC Processor Decodes MPEG Video,” Microprocessor Report, Vol. 8, No. 1, Jan. 24, 1994, pp. 16–17.
11. R. Lee and J. Huck, “64-bit and Multimedia Extensions for the PA-RISC 2.0 Architecture,” Proc. Compcon, IEEE CS Press, 1996, pp. 152–160.
12. D. Zucker, M. Flynn, and R. Lee, “Improving Performance for Software MPEG Players,” Proc. Compcon, IEEE CS Press, 1996, pp. 327–332.
13. J. Anderson, S. Amarasinghe, and M. Lam, “Data and Computation Transformations for Multiprocessors,” Proc. Fifth ACM SIGPLAN Symp. Principles and Practice of Parallel Programming, ACM, New York, 1995, pp. 166–178
14. R. Razdan and M.D. Smith, “A High-Performance Micro-architecture with Hardware-Programmable Functional Units,” Proc. 27th Ann. IEEE/ACM Int’l Symp. Microarchitecture, IEEE, Piscataway, N.J., 1994, pp. 172–180.