Compiling for instruction cache performance on a multithreaded architecture

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 419-429

  Kumar, Rakesh ^a   Tullsen, Dean M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Communication system control; Computer architecture; Computer science; Hardware; Multithreading; Operating systems; Optimizing compilers; Program processors; Surface mount technology; Yarn

Indexed keywords

APPLICATION PROGRAMS; CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; COMPUTER OPERATING SYSTEMS; COMPUTER SCIENCE; MULTITASKING; PROGRAM PROCESSORS; SURFACE MOUNT TECHNOLOGY; YARN;

COMMUNICATION SYSTEM CONTROL; COMPILE TIME; INSTRUCTION CACHES; LAY-OUT; MULTI-THREADING; MULTIPLE PROGRAM; MULTITHREADED ARCHITECTURE; OPTIMIZING COMPILERS;

PROGRAM COMPILERS;

EID: 84948983843     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176269     Document Type: Conference Paper

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