A simulation study of the switching times of 22- and 17-nm gate-length SOI nFETs on high mobility substrates and Si

IEEE Transactions on Electron Devices

Volumn 54, Issue 9, 2007, Pages 2304-2320

  Laux, Steven E ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Device simulation; Field effect transistor (FET); GaAs; Ge; In0.53Ga0.47; InP; N channel; Nonclassical CMOS; Semiconductor on insulator (SOI); Si; Switching time; Ultrathin body

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INSULATORS; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING GERMANIUM; SEMICONDUCTOR DEVICE STRUCTURES; SUBSTRATES;

BAND-TO-BAND TUNNELING; EXTRINSIC DEVICE STRUCTURES; HIGH MOBILITY SUBSTRATES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 41749085181     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.902864     Document Type: Article

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