Severe thickness variation of sub-3nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 75-76

  Liu, C T ^a   Baumann, F H ^a   Ghetti, A ^a   Vuong, H H ^a   Chang, C P ^a   Cheung, K P ^a   Colonell, J I ^a   Lai, W Y C ^a   Lloyd, E J ^a   Miner, J F ^a   Pai, C S ^a   Vaidya, H ^a   Liu, R ^a   Clemens, J T ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TRANSPORT PROPERTIES; LEAKAGE CURRENTS; MOS DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR GROWTH; TRANSMISSION ELECTRON MICROSCOPY;

GATE ELECTRODES; GATE OXIDE; SHALLOW TRENCH ISOLATION;

GATES (TRANSISTOR);

EID: 0033280504     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)