Using adaptive circuits to mitigate process variations in a microprocessor design

IEEE Design and Test of Computers

Volumn 23, Issue 6, 2006, Pages 476-483

  Fetzer, Eric S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Active clock deskew; Adaptive circuits; Cache safe technology; Dual core; Itanium microprocessor; Montecito; Power measurement; Process variation

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CACHE MEMORY; DESIGN FOR TESTABILITY;

ADAPTIVE CIRCUITS; CACHE SAFE TECHNOLOGY; ITANIUM MICROPROCESSOR; PROCESS VARIATION;

MICROPROCESSOR CHIPS;

EID: 33846074810     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.159     Document Type: Article

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