RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2006, Pages 170-171

  Ahsan, I ^a   Zamdmer, N ^a   Glushchenkov, O ^a   Logan, R ^a   Nowak, E J ^b   Kimura, H ^c   Zimmerman, J ^b   Berg, G ^a   Herman, J ^a   Maciejewski, E ^a   Chan, A ^a   Azuma, A ^d   Deshpande, S ^a   Dirahoui, B ^a   Freeman, G ^a   Gabor, A ^a   Gribelyuk, M ^a   Huang, S ^a   Kumar, M ^a   Miyamoto, K ^d   Mocuta, D ^a   Mahorowala, A ^a   Leobandung, E ^a   Utomo, H ^a   Walsh, B ^a   more..

^a IBM   (United States)

^b IBM RESEARCH   (United States)

^c SONY CORPORATION   (Japan)

^d Toshiba America Electronic Component Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PATTERN DENSITIES; PARAMETRIC SENSITIVITIES;

ELECTRIC INVERTERS; LEAKAGE CURRENTS; PARAMETER ESTIMATION; RAPID THERMAL ANNEALING; SENSITIVITY ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 41149093033     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D.Chesebro, et al., IBM Journal of Research & Dev., V39, No 1/2 1995 pp189-200.
2. P.J.Timans, et al, 'Challenges for Ulta-Shallow Junction Formation Technologies beyond the 65nm node.', IEEE International Conf. On Advanced Thermal Processing of Semiconductors.-RTP2003.
3. Th.Feudel et al, Junction Presentation on Scaling for Next Generation Microprocessors, Technical Symposium of Semicon Europe,April 2005