Process variations and process-tolerant design

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 699-704

  Bhunia, Swamp ^a   Mukhopadhyay, Saibal ^b   Roy, Kaushik ^b  

^a CASE WESTERN RESERVE UNIVERSITY   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT LEVELS; CIRCUIT PARAMETERS; CMOS DEVICES; CMOS TECHNOLOGIES; DESIGN METHODOLOGIES; DESIGN TECHNIQUES; DEVICE INTEGRATIONS; DEVICE PARAMETERS; EXPONENTIAL INCREASES; FABRICATION PROCESSES; LEAKAGE POWERS; NANOMETER SCALES; OXIDE THICKNESSES; PARAMETER VARIATIONS; PARAMETRIC YIELDS; PHYSICAL LIMITATIONS; PROCESS NODES; PROCESS PARAMETER VARIATIONS; PROCESS VARIATIONS; SEMICONDUCTOR INDUSTRIES; SHORT CHANNELS;

CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; DESIGN; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; LOGIC DESIGN; NETWORKS (CIRCUITS); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SWITCHING CIRCUITS; SWITCHING THEORY;

LOGIC CIRCUITS;

EID: 48349095147     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.131     Document Type: Conference Paper

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