Direct evaluation of gate line edge roughness impact on extension profiles in sub-50-nm n-MOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 11, 2006, Pages 2755-2763

  Fukutome, Hidenobu ^a   Momiyama, Youichi ^a   Kubo, Tomohiro ^a   Tagawa, Yukio ^a   Aoyama, Takayuki ^a   Arimoto, Hiroshi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Line edge roughness (LER); MOSFETs; Nitrogen coimplantation; Two dimensional (2 D) carrier profile

Indexed keywords

GATES (TRANSISTOR); ION IMPLANTATION; NITROGEN; SCANNING TUNNELING MICROSCOPY; SURFACE ROUGHNESS;

CARRIER PROFILE; FLUCTUATIONS; LINE EDGE ROUGHNESS (LER); NITROGEN COIMPLANTATION;

MOSFET DEVICES;

EID: 33750601335     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.882784     Document Type: Article

References (11)

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