Accurate on-chip interconnect evaluation: A time-domain technique

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 5, 1999, Pages 623-631

  Soumyanath, K ^a,b   Borkar, Shekhar ^a   Zhou, Chunyan ^a   Boechel, Bradley A ^a  

^a INTEL CORPORATION   (United States)

^b TUFTS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; METALLIZING; SEMICONDUCTOR DEVICE MODELS; SIGNAL NOISE MEASUREMENT; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

ON-CHIP INTERCONNECT EVALUATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032635504     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760372     Document Type: Article

References (7)

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