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Volumn , Issue , 2006, Pages 1443-1446

Multilevel flash memory on-chip error correction based on trellis coded modulation

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; MICROPROCESSOR CHIPS; PHASE MODULATION; SILICON; TRELLIS CODES;

EID: 34547312255     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (12)

References (9)
  • 1
    • 0032304222 scopus 로고    scopus 로고
    • Nonvolatile multilevel memories for digital applications
    • Dec
    • B. Ricco et al., "Nonvolatile multilevel memories for digital applications," Proceedings of the IEEE, vol. 86, pp. 2399-2423, Dec. 1998.
    • (1998) Proceedings of the IEEE , vol.86 , pp. 2399-2423
    • Ricco, B.1
  • 2
    • 4344701872 scopus 로고    scopus 로고
    • On-chip error correcting techniques for new-generation Flash memories
    • April
    • S. Gregori, A. Cabrini, O. Khouri, and G. Torelli, "On-chip error correcting techniques for new-generation Flash memories," Proceedings of the IEEE, vol. 91, pp. 602-616, April 2003.
    • (2003) Proceedings of the IEEE , vol.91 , pp. 602-616
    • Gregori, S.1    Cabrini, A.2    Khouri, O.3    Torelli, G.4
  • 5
    • 0023295985 scopus 로고
    • Trellis-coded modulation with redundant signal sets Part I, II
    • Feb
    • G. Ungerboeck, "Trellis-coded modulation with redundant signal sets Part I, II," IEEE Communications Magazine, vol. 25, pp. 5-21, Feb. 1987.
    • (1987) IEEE Communications Magazine , vol.25 , pp. 5-21
    • Ungerboeck, G.1
  • 7
    • 0023383214 scopus 로고
    • Trellis-coded modulation with multidimensional constellations
    • July
    • L. F Wei, "Trellis-coded modulation with multidimensional constellations," IEEE Transactions on Information Theory, vol. 33, pp. 483-501, July 1987.
    • (1987) IEEE Transactions on Information Theory , vol.33 , pp. 483-501
    • Wei, L.F.1
  • 9
    • 0026153976 scopus 로고
    • High-speed parallel Viterbi decoding: Algorithm and VLSI-architecture
    • May
    • G. Fettweis and H. Meyr, "High-speed parallel Viterbi decoding: algorithm and VLSI-architecture," IEEE Communications Magazine, vol. 29, pp. 46-55, May 1991.
    • (1991) IEEE Communications Magazine , vol.29 , pp. 46-55
    • Fettweis, G.1    Meyr, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.