Area efficient parallel decoder architecture for long BCH codes

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 5, Issue , 2004, Pages

  Chen, Yanni ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTATIONAL COMPLEXITY; FAST FOURIER TRANSFORMS; OPTICAL COMMUNICATION; PROBLEM SOLVING; SEARCH ENGINES;

CHIENE SEARCH; HARDWARE COMPLEXITY; SYNDROME GENERATORS;

CODES (SYMBOLS);

EID: 4544229949     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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3. S. B. Wicker, Error control systems for digital communication and storage, Upper saddle river: NJ: Prentice-Hall, 1995.
4. H. C. Chang, C. B. Shung, and C. Y. Lee, "A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications," IEEE J. Solid State Circuits, vol. 36, pp. 229-238, Feb. 2001.
5. C. Paar, "Optimized arithmetic for Reed-Solomon encoders," IEEE Proc. of ISIT'97, pp. 250, 1997.
6. M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, "Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination," IEEE Trans. on Computer-Aided Design, vol. 15, no. 2, pp. 151-165, Feb. 1996.