Fast and compact error correcting scheme for reliable multilevel flash memories

Proceedings of the 8th IEEE International On-Line Testing Workshop, IOLTW 2002

Volumn , Issue , 2002, Pages 221-225

  Rossi, D ^a   Metra, C ^a   Ricco B ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COST REDUCTION; ERRORS; FLASH MEMORY; MATRIX ALGEBRA; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS;

AREA OVERHEAD; CORRECTING CODES; CORRECTION ABILITY; ERROR CORRECTING SCHEME; MATRIX WEIGHT; MEMORY ACCESS TIME; MULTILEVEL FLASH MEMORY; PARITY CHECK MATRICES;

ERROR CORRECTION;

EID: 84962736050     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2002.1030222     Document Type: Conference Paper

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