An overview of logic architectures inside flash memory devices

Proceedings of the IEEE

Volumn 91, Issue 4, 2003, Pages 569-580

  Silvagni, Andrea ^b   Fusillo, Giuseppe ^b   Ravasio, Roberto ^a,b   Picca, Massimiliano ^b   Zanardi, Stefano ^b  

^a IEEE

^b STMICROELECTRONICS   (Italy)

Author keywords

Burst mode; Error correction code (ECC); Multilevel cell; NOR Flash memory; Page mode; Program erase controller; Redundancy; Unerasable programmable ROM (UPROM)

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER SYSTEMS PROGRAMMING; DATA STORAGE EQUIPMENT; ERROR CORRECTION; INTERFACES (COMPUTER); LOGIC CIRCUITS; PROM; REDUNDANCY;

BURST MODE; ERROR CORRECTION CODE (ECC); MULTILEVEL CELL; NOR FLASH MEMORY; PAGE MODE; PROGRAM/ERASE CONTROLLER; UNERASABLE PROGRAMMABLE ROM (UPROM);

FLASH MEMORY;

EID: 11144235303     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2003.811707     Document Type: Review

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