High-speed parallel sensing scheme for multi-level non-volatile memories

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 1997, Pages 96-101

  Calligaro, Cristiano ^a   Gastaldi, Roberto ^a   Manstretta, Alessandro ^a   Torelli, Guido ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER TESTING; PARALLEL PROCESSING SYSTEMS; THRESHOLD ELEMENTS;

ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM); HIGH SPEED PARALLEL SENSING SCHEME; MULTILEVEL NONVOLATILE MEMORIES (NV MLM);

PROM;

EID: 0030690744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)