Scan-based transition fault testing-Implementation and low cost test challenges

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 1120-1129

  Saxena, Jayashree ^a   Butler, Kenneth M ^a   Gatt, John ^a   Raghuraman, R ^a   Kumar, Sudheendra Phani ^a   Basu, Supatra ^a   Campbell, David J ^a   Berech, John ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; COST BENEFIT ANALYSIS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; SCANNING;

LOW COST TEST EQUIPMENT; SCAN BASED DELAY TESTING; SCAN BASED TRANSITION FAULT TESTING;

SEMICONDUCTOR DEVICE TESTING;

EID: 0036444572     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041869     Document Type: Article

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