Pattern generation and estimation for power supply noise analysis

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 439-444

  Nourani, Mehrdad ^a   Tehranipoor, Mohammad ^b   Ahmed, Nisar ^c  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

^b UNIVERSITY OF MARYLAND BALTIMORE COUNTY   (United States)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC PATTERN GENERATION; DEEP SUBMICRON CMOS; GREEDY HEURISTICS; INSTANTANEOUS CURRENT; INTERNAL CIRCUITRY; MAXIMUM-SWITCHING ACTIVITY; PATTERN GENERATION; POWER SUPPLY NOISE ANALYSIS;

CMOS INTEGRATED CIRCUITS; SPICE;

INTEGRATED CIRCUIT TESTING;

EID: 84886456897     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.65     Document Type: Conference Paper

References (12)

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