High-frequency, at-speed scan testing

IEEE Design and Test of Computers

Volumn 20, Issue 5, 2003, Pages 17-25

  Lin, Xijiang ^a   Press, Ron ^a   Rajski, Janusz ^a   Reuter, Paul ^a   Rinderknecht, Thomas ^a   Swanson, Bruce ^a   Tamarapalli, Nagesh ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DEFECTS; ELECTRIC PROPERTIES; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; SHIFT REGISTERS; TIMING CIRCUITS;

AT-SPEED SCAN TESTING; AUTOMATIC TEST PATTERN GENERATION; MULTIPLE-INPUT SHIFT REGISTER; ON-CHIP CLOCK; PSEUDO-RANDOM PATTERN GENERATOR;

INTEGRATED CIRCUIT TESTING;

EID: 0142039802     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1232252     Document Type: Article

References (10)

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