Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits

Proceedings of the European Test Workshop

Volumn 2003-January, Issue , 2003, Pages 105-110

  Liau, E ^a   Schmitt Landsiedel, D ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Automatic test equipment; Circuit noise; Energy consumption; Genetic algorithms; Neural networks; Noise generators; Power generation; Power supplies; Silicon; Switching circuits

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; CHOPPERS (CIRCUITS); CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; EQUIPMENT TESTING; NETWORKS (CIRCUITS); NEURAL NETWORKS; NOISE GENERATORS; POWER GENERATION; SILICON; SWITCHING CIRCUITS;

AUTOMATIC TEST EQUIPMENT; CIRCUIT NOISE; INSTANTANEOUS CURRENT; NEURAL NETWORK (NN); POWER SUPPLY; POWER-SUPPLY NOISE; WORST CASE INPUTS; WORST CASE PATTERN;

GENETIC ALGORITHMS;

EID: 49749101050     PISSN: 15301877     EISSN: 15581780     Source Type: Conference Proceeding    
DOI: 10.1109/ETW.2003.1231676     Document Type: Conference Paper

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