Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 416-425

  Krstić, Angela ^a,b   Jiang, Yi Min ^a,c   Cheng, Kwang Ting ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c SYNOPSYS INC   (United States)

Author keywords

ATPG; Deep submicrometer; Delay testing; Electromigration; Noise analysis; Testing; Timing analysis; VLSI

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; DEEP SUBMICROMETER DESIGN; DELAY TESTING; DYNAMIC TIMING ANALYSIS; NOIS ANALYSIS;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTROMIGRATION; INTEGRATED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035273397     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913759     Document Type: Article

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