A novel framework for faster-than-at-speed delay test considering IR-drop effects

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 198-203

  Ahmed, Nisar ^a   Tehranipoor, Mohammad ^a   Jayaram, Vinay ^b  

^a UNIVERSITY OF CONNECTICUT   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AT SPEED TESTING; AT-SPEED; AUTOMATIC TEST PATTERN GENERATION (ATPG) TOOL; CASE STUDIES; COMPUTER-AIDED DESIGN; DELAY DEFECTS; DELAY TESTING; INTERNATIONAL CONFERENCES; IR DROPS; PERFORMANCE DEGRADATION; TEST FREQUENCIES;

DESIGN; DROPS; FLUID MECHANICS; PHOTOACOUSTIC EFFECT; SULFATE MINERALS; TURBULENT FLOW;

TESTING;

EID: 46149125958     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320136     Document Type: Conference Paper

References (14)

1. J. Saxena, K. M. Butler, J. Gatt, R. Raghuraman, S. P. Kumar, S. Basu, D. J. Campbell, J. Berech, "Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges," in Proc. International Test Conference (ITC'02), pp. 1120 - 1129, Oct. 2002.
2. X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, "High-Frequency, At-Speed Scan Testing," IEEE Design & Test of Computers, pp. 17-25, Sep-Oct 2003.
3. B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, "On hazard-free patterns for fine-delay fault testing," in Proc. Int. Test Conf. (ITC'04), pp. 213-222, 2004.
4. Cadence Inc., "Encounter True-time TestATPG", http://www.cadence.com, 2006.
5. H. Hao and E.J. McCluskey, "Very-low-voltage testing for weak CMOS logic ICs," in Proc. Int. Test Con. (ITC'93), pp. 275-284, 1993.
6. R. Foster, "Why Consider Screening, Burn-In, and 100-Percent Testing for Commercial Devices?," IEEE Transactions on Manufacturing Technology, vol. 5, no. 3, pp. 52-58, 1976.
7. P. Gupta and M. S. Hsiao, "ALAPTF: A new transition fault model and the ATPG algorithm," in Proc. Int. Test Conf. (ITC'04), pp. 1053-1060, 2004.
8. W. Qiu, J. Wang, D. M. H. Walker, D. Reddy, X. Lu, Z. Li, W. Shi and H. Balichandran, "K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits," in Proc. Int. Test Conf. (ITC'04), pp. 223-231, 2004.
9. B.N. Lee, L. C. Wang and M. S. Abadir, "Reducing pattern delay variations for screening frequency dependent defects," in Proc. VLSI Test Symp. (VTS'05), pp.153-160, 2005.
10. Synopsys Inc., "User Manuals for SYNOPSYS Toolset Version 2005.09," Synopsys, Inc., 2005.
11. Cadence Inc., "User Manuals for Cadence Encounter Tool set Version 2004.10," Cadence, Inc., 2004.
12. http://crete.cadence.com, 0.18μm standard cell GSCLib library version 2.0, Cadence, Inc., 2005.
13. N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, "At-Speed Transition Fault Testing With Low Speed Scan Enable," in Proc. IEEE VLSI Test Svmp. (VTS'05), pp. 42-47, 2005.
14. B. Benware, C. Schuermyer, N. Tamarapalli, Kun-Han Tsai, S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy, "Impact of multiple-detect test patterns on product quality," in Proc. Int. Test Conf. (ITC'03), pp. 1031-1040, 2003.