Static Verification of Test Vectors for IR Drop Failure

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 760-764

  Kokrady, Aman A ^a   Ravikumar, C P ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CROSSTALK; DELAY CIRCUITS; ELECTRIC POTENTIAL; ELECTRONIC EQUIPMENT TESTING; ERROR ANALYSIS; MICROPROCESSOR CHIPS; PROBLEM SOLVING; SWITCHING; VECTORS;

PROCESS VOLTAGE TEMPERATURE (PVT); TEST VECTOR GENERATION; TRANSITION DELAY TESTS;

LOGIC GATES;

EID: 0348040097     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159762     Document Type: Conference Paper

References (15)

1. G. Bai, S. Bobba, and I.N. Hajj. "Power Bus Maximum Voltage Drop in Digital VLSI Circuits." In Proceedings of International Symposium on Quality of Electronic Design, pages 263-268, March 2000.
2. D. Bhattacharya, P. Agrawal, V.D. Agrawal, "Test generation for path delay faults using Binary Decision Diagrams," IEEE Transactions on Computers, March 1995
3. Michael L. Bushnell, Vishwani D. Agrawal. Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, November 2000
4. R. Chaudhry, D. Blaauw, R. Panda, T. Edwards, "Current signature compression for IR-Drop analysis", Proceedings of IEEE design Automation conference, 2000.
5. D.I. Cheng, K.T. Cheng, D.C. Wang, M.M. Sadowska. "Hybrid methodologies for switching activities estimation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 17, No.4, April 1998.
6. th IEEE Design Automation Conference, June 25-29, 1989.
7. Haroun, A.J., F. Routabi, B. Khalili, "Power estimation tool for sub-micron VLSI circuits". In IEEE International Conference on Computer Aided design, 1992
8. th IEEE/ACM Design Automation Conference, pages 384-388, 1993.
9. H. Kriplani, F. Najm, and I. Hajj. Worst Case Voltage Drop in Power and Ground Busses in CMOS VLSI Circuits. SRC TECHON'93 Conference, Atlanta, GA, pp. 402-404, September 28-30, 1993.
10. A. Krstic, K. T. Cheng "Vector generation for maximum instantaneous current through supply lines for CMOS circuits", Proceedings of IEEE design Automation conference, 1997
11. L R Liu, H.C. Chen, H. C. Du, "The calculation of signal stable ranges in combinational circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 1994
12. Synopsys, Inc. Prime Time User Manual, 2002.
13. Synopsys, Inc. Power Compiler User Manual, 2002.
14. Synopsys, Inc. AstroRail User manual, 2002.
15. Texas Instruments India. Toggle Frequency Calculator Reference Manual, 2003.