Fabrication of strained Si channel PMOSFET on thin relaxed Si 1-xGex virtual substrate

Microelectronics Journal

Volumn 35, Issue 12, 2004, Pages 969-971

  Mei, Ding Lei ^a   Li, Jing Chun ^a   Zhang, Jing ^b   Xu, Wan Jing ^b   Tan, Kai Zhou ^b   Yang, Mo Hua ^a  

^a UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA   (China)

^b National Laboratory of Analog Integrated Circuits   (China)

Author keywords

Low temperature (LT) Si; SiGe; Strain relaxation; Threading dislocation

Indexed keywords

ATOMIC FORCE MICROSCOPY; CHEMICAL VAPOR DEPOSITION; DOPING (ADDITIVES); EPITAXIAL GROWTH; GERMANIUM; OXIDATION; POLYSILICON; RELAXATION PROCESSES; STRAIN;

LOW-TEMPERATURE; SIGE; STRAIN RELAXATION; THREADING DISLOCATION;

MOSFET DEVICES;

EID: 9544244804     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2004.07.011     Document Type: Article

References (2)

1. H. Wentao, L. Guangli, S. Jin, D. Ning, C. Peiyi, Q. Peixin, HV/CVD grown relaxed SiGe buffer layers for SiGe HMOSFETs, Tsinghua Science and Technology 8 (2) (2003) 130.
2. E.A. Fitzgerald, M.L. Lee, C.W. Leitz, D.A. Antoniadis, MOSFET channel engineering using strained Si, SiGe, and Ge channel, ECS Meeting Proceedings, Paris, France, April 29, 2003.