Clock power issues in system-on-a-chip designs

Proceedings - IEEE Computer Society Workshop on VLSI 1999: System Design: Towards System-on-a-Chip Paradigm, VLSI 1999

Volumn , Issue , 1999, Pages 48-53

  Chen, R Y ^a   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURAL DESIGN; CLOCKS; ELECTRIC CLOCKS; ELECTRIC POWER UTILIZATION; INTELLECTUAL PROPERTY CORE; INTERNET PROTOCOLS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP; VLSI CIRCUITS;

CIRCUIT DESIGNS; CLOCK DISTRIBUTION; CLOCK NETWORK; CLOCK POWER CONSUMPTION; LOGIC STYLE; MULTIPLE FREQUENCY; POWER MODEL; SYSTEM-ON-A-CHIP DESIGNS;

INTEGRATED CIRCUIT DESIGN;

EID: 0002982462     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.1999.760472     Document Type: Conference Paper

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