Analysis and design of optimal combinational compactors [logic test]

Proceedings of the IEEE VLSI Test Symposium

Volumn 2003-January, Issue , 2003, Pages 101-106

  Wohl, P ^a   Huisman, L ^b  

^a SYNOPSYS INC   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Automatic testing; Built in self test; Circuit testing; Costs; Delay; Graph theory; Logic testing; Pins; Robustness; Signal analysis

Indexed keywords

AUTOMATIC TESTING; COST BENEFIT ANALYSIS; COSTS; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; ROBUSTNESS (CONTROL SYSTEMS); SIGNAL ANALYSIS; VLSI CIRCUITS;

CIRCUIT TESTING; DELAY; INTERNAL SIGNALS; LOGIC BUILT-IN SELF TEST; LOGIC TESTING; PINS; SIGNATURE ANALYZERS; TEST ARCHITECTURE;

BUILT-IN SELF TEST;

EID: 84943549146     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2003.1197639     Document Type: Conference Paper

References (17)

1. Semiconductor Industry Association (SIA), International Technology Roadmap for Semiconductors (ITRS), 1999.
2. M. Abramovici, M.A. Breuer, A.D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.
3. E.B. Eichelberger, E. Lindbloom, J.A. Waicukauski, T.W. Williams, Structured Logic Testing, Prentice-Hall, 1991.
4. G. Hetherington, T. Fryars, N. Tamarapalli, M. Kassab, A. Hassan, J. Rajski, "Logic BIST for Large Industrial Designs: Real Issues and Case Studies", International Test Conference 1999, pp.358-367.
5. H.J. Nadig, "Testing a Microprocessor Product Using a Signature Analysis", International Test Conference 1978, pp.159-169.
6. V.D. Agrawal, C.R. Kime, K.K. Saluja, "A Tutorial on Built-In Self-Test, Part 1: Principles", IEEE Design & Test 1993, Vol. 10, No.1, pp. 73-82.
7. P.H. Bardell, W.H. McAnney, "Self-Testing of Multichip Logic Modules", International Test Conference 1982, pp.200-204.
8. P.H. Bardell, W.H. McAnney, J. Savir, Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987.
9. S. Pilarski, T. Kameda, A Probabilistic Analysis of Test-Response Compaction, IEEE Computer Society Press, 1995.
10. T.W. Williams, W. Daehn, M. Gruetzner, C.W. Starke, "Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials", International Test Conference 1986, pp.282-288.
11. K. Chakrabarty, B.T. Murray, J.P. Hayes, "Optimal Space Compaction of Test Responses", International Test Conference 1995, pp.834-843.
12. K. Chakrabarty, "Zero-aliasing Space Compaction using Linear Compactors with Bounded Overhead", IEEE Trans. CAD, Vol 17, No. 5, May 1998, pp. 452-457.
13. P. Wohl, J.A. Waicukauski, T.W. Williams, "Design of Compactors for Signature-Analyzers in Built-In Self Test", International Test Conference 2001, pp.54-63.
14. S. Mitra, K.S. Kim, "X-Compact An Efficient Response Compaction Technique for Test Cost Reduction", International Test Conference 2002, pp.311-320.
15. J. A. Bondy and U.S.R. Murty, Graph Theory with Applications, North Holland, 1976.
16. B. Bollobas, Modern Graph Theory, Springer, 1998.
17. G. Royle, Cages of higher valency, http://www.cs.uwa.edu.au/~gordon/cages/allcages.html