Test response compaction using multiplexed parity trees

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 11, 1996, Pages 1399-1408

  Chakrabarty, Krishnendu ^a,b   Hayes, John P ^a,b  

^a Boston University   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; MULTIPLEXING; TREES (MATHEMATICS);

FANOUT INSERTION; MULTIPLEXED PARITY TREE; OUTPUT SELECTION; TEST RESPONSE COMPACTION;

VLSI CIRCUITS;

EID: 0030285141     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.543772     Document Type: Article

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