Synthesis of zero-aliasing elementary-tree space compactors

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 70-77

  Pouya, B ^a   Touba, N A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMPRESSION; DESIGN FOR TESTABILITY; ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; LOGIC CIRCUITS; TREES (MATHEMATICS);

SPACE COMPACTORS;

INTEGRATED CIRCUIT TESTING;

EID: 0032310133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)