Efficient compression and application of deterministic patterns in a logic BIST architecture

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 566-569

  Wohl, Peter ^a   Waicukauski, John A ^a   Patel, Sanjay ^a   Amin, Minesh B ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Self test (BIST); Test generation (ATPG)

Indexed keywords

COMPUTER ARCHITECTURE; DATA COMPRESSION; FEEDBACK CONTROL; PATTERN MATCHING; SHIFT REGISTERS;

LINEAR FEEDBACK SHIFT REGISTERS (LFSR);

DIGITAL SIGNAL PROCESSING;

EID: 0043136599     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775972.775976     Document Type: Conference Paper

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