-
1
-
-
0032306079
-
Testing Embedded-Core Based System Chips
-
Y. Zorian, E. J. Marinissen and S. Dey, "Testing Embedded-Core Based System Chips", in ITC, pp. 130-143, 1998.
-
(1998)
ITC
, pp. 130-143
-
-
Zorian, Y.1
Marinissen, E.J.2
Dey, S.3
-
2
-
-
0032206192
-
Optimal Space Compaction of Test Responses
-
November
-
K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal Space Compaction of Test Responses", IEEE TCOMP, vol. 47, n. 11, pp. 1171-1187, November 1998.
-
(1998)
IEEE TCOMP
, vol.47
, Issue.11
, pp. 1171-1187
-
-
Chakrabarty, K.1
Murray, B.T.2
Hayes, J.P.3
-
3
-
-
0034994934
-
Design of Parameterizable Error-Propagating Space Compactors for Response Observation
-
A. Morosov, K. Chakrabarty, M. Gossel and B. Bhattacharya, "Design of Parameterizable Error-Propagating Space Compactors for Response Observation", in VTS, pp. 48-53, 2001.
-
(2001)
VTS
, pp. 48-53
-
-
Morosov, A.1
Chakrabarty, K.2
Gossel, M.3
Bhattacharya, B.4
-
4
-
-
0032063899
-
Zero-aliasing Space Compaction Using Linear Compactors with Bounded Overhead
-
May
-
K. Chakrabarty, "Zero-aliasing Space Compaction Using Linear Compactors with Bounded Overhead", IEEE TCAD, vol. 17, n. 5, pp. 452-457, May 1998.
-
(1998)
IEEE TCAD
, vol.17
, Issue.5
, pp. 452-457
-
-
Chakrabarty, K.1
-
5
-
-
0030285141
-
Test Response Compaction Using Multiplexed Parity Trees
-
Nov
-
K. Chakrabarty and J. P. Hayes, "Test Response Compaction Using Multiplexed Parity Trees", IEEE TCAD, vol. 15, n. 11, pp. 1399-1408, Nov 1996.
-
(1996)
IEEE TCAD
, vol.15
, Issue.11
, pp. 1399-1408
-
-
Chakrabarty, K.1
Hayes, J.P.2
-
7
-
-
0036761475
-
Efficient Construction of Aliasing-Free Compaction Circuitry
-
September/October
-
O. Sinanoglu and A. Orailoglu, "Efficient Construction of Aliasing-Free Compaction Circuitry", IEEE Micro, pp. 82-92, September/October 2002.
-
(2002)
IEEE Micro
, pp. 82-92
-
-
Sinanoglu, O.1
Orailoglu, A.2
-
8
-
-
0036058081
-
On Output Response Compression in the Presence of Unknown Output Values
-
I. Pomeranz, S. Kundu and S. M. Reddy, "On Output Response Compression in the Presence of Unknown Output Values", in DAC, pp. 255-258, 2002.
-
(2002)
DAC
, pp. 255-258
-
-
Pomeranz, I.1
Kundu, S.2
Reddy, S.M.3
-
9
-
-
0035680657
-
Design of Compactors for Signature Analyzers in Built-in Self-Test
-
P. Wohl, J. A. Waicukauski and T. W. Williams, "Design of Compactors for Signature Analyzers in Built-in Self-Test", in ITC, pp. 54-63, 2001.
-
(2001)
ITC
, pp. 54-63
-
-
Wohl, P.1
Waicukauski, J.A.2
Williams, T.W.3
-
10
-
-
0036443042
-
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
-
S. Mitra and K. S. Kim, "X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction", in ITC, pp. 311-320, 2002.
-
(2002)
ITC
, pp. 311-320
-
-
Mitra, S.1
Kim, K.S.2
-
12
-
-
0032592908
-
Diagnosis of Scan Cells in BIST Environment
-
J. Rajski and J. Tyszer, "Diagnosis of Scan Cells in BIST Environment", IEEE TCOMP, vol. 48,n. 7, pp. 724-731, 1999.
-
(1999)
IEEE TCOMP
, vol.48
, Issue.7
, pp. 724-731
-
-
Rajski, J.1
Tyszer, J.2
-
13
-
-
38749131846
-
Diagnosis Oriented Test Pattern Generation
-
P. Camurati, A. Lioy, P. Prinetto and M. S. Reorda, "Diagnosis Oriented Test Pattern Generation", in European DAC, pp. 470-474, 1990.
-
(1990)
European DAC
, pp. 470-474
-
-
Camurati, P.1
Lioy, A.2
Prinetto, P.3
Reorda, M.S.4
-
14
-
-
0002946363
-
Combinational Profiles of Sequential Benchmark Circuits
-
May
-
F. Brglez, D. Bryan and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits", IEEE ISCAS, vol. 14, n. 2, pp. 1929-1934, May 1989.
-
(1989)
IEEE ISCAS
, vol.14
, Issue.2
, pp. 1929-1934
-
-
Brglez, F.1
Bryan, D.2
Kozminski, K.3
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