Zero-aliasing space compaction using linear compactors with bounded overhead

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 5, 1998, Pages 452-457

  Chakrabarty, Krishnendu ^a  

^a BOSTON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GRAPH THEORY; INTEGRATED CIRCUIT TESTING; SHIFT REGISTERS;

BUILT IN SELF TEST (BIST); LINEAR COMPACTORS; MULTIPLE INPUT SIGNATURE REGISTERS (MISR);

INTEGRATED CIRCUIT LAYOUT;

EID: 0032063899     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703941     Document Type: Article

References (25)

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