Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC™ instruction set architecture

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 3-8

  Tendolkar, N ^a   Raina, R ^a   Woltenberg, R ^a   Lin, Xijiang ^b   Swanson, B ^b   Aldrich, G ^b  

^a MOTOROLA INC   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay; Latches; Microprocessors; Pins; Switches; Test pattern generators

Indexed keywords

CLOCKS; COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; SWITCHES; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; DELAY; PINS; TEST PATTERN GENERATOR;

AUTOMATIC TEST PATTERN GENERATION;

EID: 84948408811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011103     Document Type: Conference Paper

References (9)

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