ATPG for heat dissipation minimization during test application

IEEE Transactions on Computers

Volumn 47, Issue 2, 1998, Pages 256-262

  Wang, Seongmoon ^a   Gupta, Sandeep K ^a  

^a University of Southern California   (United States)

Author keywords

Combinational ATPG; Heat dissipation; PODEM; Switching activity; Testing

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; HEAT LOSSES;

AUTOMATIC TEST PATTERN GENERATORS (ATPG);

INTEGRATED CIRCUIT TESTING;

EID: 0032003411     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.663775     Document Type: Article

References (15)

1. M. Abramovici, M.A. Breuer, and A.D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
2. S. Bhatia and N.K. Jha, "Synthesis for Parallel Scan: Applications to Partial Scan and Robust Path-Delay Fault Testability," IEEE Trans. Computer-Aided Design of Integrated Circuit and System, vol. 15, Feb. 1996.
3. S. Chakravarty and V.P. Dabholkar, "Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application," Proc. Third Asian Test Symp., 1994.
4. D.A. Doane and P.D. Franzon, Multchip Module Technologies and Alternatives: The Basics. New York: Van Nostrand Reinhold, 1992.
5. P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. Computers, vol. 30, no. 3, Mar. 1981.
6. L.H. Goldstein, "Controllability/Observability Analysis of Digital Circuits," IEEE Trans. Circuits and Systems, vol. 26, pp. 685-693, Sept. 1979.
7. L.H. Goldstein and E.L. Thigpen, "SCOAP: Sandia Controllability/Observability Analysis Program," Proc. IEEE-ACM Design Automation Conf., pp. 190-196, 1980.
8. R. Gupta, R. Gupta, and M.A. Breuer, "The BALLAST Methodology for Structured Partial Scan Design," IEEE Trans. Computers, vol. 39, no. 4, Apr. 1990.
9. D.K. Pradhan and J. Saxena, "Design for Testablility Scheme to Reduce Test Application in Full Scan," Proc. VLSI Testing Symp., pp. 55-60, 1992.
10. A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks," Proc. IEEE Int'l Conf. Computer-Aided Design, pp. 402-407, Nov. 1992.
11. S. Wang and S.K. Gupta, "ATPG for Heat Dissipation Minimization During Test Application," Proc. IEEE Int'l Test Conf., pp. 250-258, Oct. 1994.
12. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, second ed. Reading, Mass.: Addison-Wesley, 1992.
13. Y. Zorian, Private Communication.
14. Y. Zorian, "A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary Scan," Proc. IEEE Int'l Conf. Computer Design, 1992.
15. Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," Proc. VLSI Testing Symp., pp. 4-9, 1993.