Peak-power reduction for multiple-scan circuits during test application

Proceedings of the Asian Test Symposium

Volumn , Issue , 2000, Pages 453-458

  Lee, Kuen Jong ^a   Huang, Tsung Chu ^a   Chen, Jih Jeen ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLE SCAN CIRCUITS; PEAK POWER REDUCTION;

DESIGN FOR TESTABILITY; LOGIC DESIGN;

LOGIC CIRCUITS;

EID: 0034505824     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. Lee Whetsel. Addressable Test Ports-an Approach to Testing Embedded Cores. In Int'l Test Coni, pages 1055-1064, 1999.
2. M. Abramovici, M.A. Breuer, and A.D. Friedman. Digital system testing and testable design. Computer Science Press, 1990.
3. Y. Zorian. A Distributed BIST Control Scheme for Complex VLSI Devices. In VLSI Test Symp., pages 4-9, 1993.
4. S. Gerstendorfer and H.-J. Wunderlich. Minimized Power Consumption for Scan-based BIST. In Int'l Test Conf., pages 77-84, 1999.
5. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. In Asian Test Symp., pages 89-94, 1999.
6. S. Chakravarty and V.P. Dabholkar. Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application. In IEEE Asian Test Symp., pages 324-329, 1994.
7. S. Wang and S. K. Gupta. LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation. In Int'l Test Coni, pages 85-94, 1999.
8. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. A Test Vector Inhibiting Technique for Low Energy BIST Design. In VLSI Test Symp., pages 407-412, 1999.
9. Seongmoon Wang and Sandeep K. Gupta. DS-LFSR: A New BIST TPG for Low Heat Dissipation. In Int'l Test Coni, pages 848-857, 1997.
10. P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac. Reduction of Power Consumption during Test Application by Test Vector Ordering. Electronics Letters, 33(21):1752-1754, Oct. 1997.
11. F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda. A Test Pattern Generation Methodology for Low Power Consumption. In VLSI Test Symp., pages 453-457, 1998.
12. Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, and Sudhakar Reddy. Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application. IEEE Trans, on Computer-Aided Design, 17(12):1325-1333, Dec. 1998.
13. Tsung-Chu Huang and Kuen-Jong Lee. An Input Control Technique for Power Reduction in Scan Circuits During Test Application. In The Eighth Asian Test Symposium, pages 315-320, Nov. 1999.
14. R. M. Chou, K. K. Saluja, and V. D. Agrawal. Power Constraint Scheduling of Tests. In Proc. Conf. on VLSI Design, pages 271-274, 1994.
15. R. M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling Tests for VLSI Systems Under Power Constraints. IEEE Trans, on VLSI Systems, 5(2):175-185, Jun. 1997.
16. K.-J. Lee, J.-J. Chen, and C.-H. Huang. Broadcasting Test Patterns to Multiple Circuits. IEEE Trans, on CAD, 18(12):1793-1802, Dec. 1999.
17. K. I. Diamantaras and N.K. Jha. A New Transition Count Method for Testing of Logic Circuits. IEEE Trans. CAD, 10(3):407-410, Mar. 1991.
18. K. Roy and S. Prasad. Circuit Activity Based Logic Synthesis for Low Power Reliable Operations. IEEE Trans. VLSI Systems, 1(4):503-513, Dec. 1993.
19. K.-J. Lee, M.-H. Lu, and J.-F. Wang. A Systematic Method to Classify Scan Cells. In Asian Test Symp., pages 219-224, 1993.
20. E. B. Eichelberger and T. W. Williams. A Logic Design Structure for LSI Testing. In Proc. Design Automation Conf., pages 462-468, 1977.
21. C. T. Glover and M. R. Mercer. A Method of Delay Fault Test Generation. In Proc. Design Automation Conf., pages 83-90, 1988.