Test pattern generation methodology for low power consumption

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1998, Pages 453-457

  Corno, F ^a   Prinetto, P ^a   Rebaudengo, M ^a   Reorda, M S ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EFFICIENCY; ELECTRIC FAULT LOCATION; ENERGY DISSIPATION; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; REDUNDANCY;

TEST PATTERN GENERATION;

SEQUENTIAL CIRCUITS;

EID: 0032317778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)