Generation of low power dissipation and high fault coverage patterns for scan-based BIST

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 834-843

  Wang, Seongmoon ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; CORRELATION METHODS; ELECTRIC POWER MEASUREMENT; LOGIC DESIGN; RANDOM PROCESSES; SCANNING; SWITCHING CIRCUITS;

CIRCUIT UNDER TEST; HIGH FAULT COVERAGE PATTERNS; LOW POWER DISSIPATION; TEST PATTERN GENERATOR;

BUILT-IN SELF TEST;

EID: 0036443053     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041837     Document Type: Article

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