Power driven chaining of flip-flops in scan architectures

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 796-803

  Bonhomme, Y ^a   Girard, P ^a   Landrault, C ^a   Pravossoudovitch, S ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; DATA COMPRESSION; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; SIMULATED ANNEALING;

AUTOMATIC TEST EQUIPMENT; AUTOMATIC TEST PATTERN GENERATION; INTERLEAVING SCHEME; SCAN CELL ORDERING; SCAN PATH SEGMENTATION TECHNIQUE; STATIC COMPACTION TECHNIQUE; TWO CLOCK SCHEME MODIFICATION TECHNIQUE;

INTEGRATED CIRCUIT TESTING;

EID: 0036443052     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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