Intrinsic shortest path length: A new, accurate a priori wirelength estimator

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 173-180

  Kahng, Andrew B ^a   Reda, Sherief ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTRINSIC SHORTEST PATH LENGTH (ISPL); MULTI PIN NETS; NODE PAIRS; PRIORI GLOBAL INTERCONNECT PREDICTION; WIRELENGTH ESTIMATORS;

MATHEMATICAL MODELS; PARAMETER ESTIMATION; PREDICTIVE CONTROL SYSTEMS; VLSI CIRCUITS;

INTERCONNECTION NETWORKS;

EID: 33750905426     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560059     Document Type: Conference Paper

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