Pre-layout wire length and congestion estimation

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 582-587

  Liu, Qinghua ^a   Marek Sadowska, Malgorzata ^a  

^a University of California   (United States)

Author keywords

Congestion; Prediction; Wire Length

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER AIDED ENGINEERING; ELECTRIC WIRE; LOGIC DESIGN; STRUCTURAL DESIGN; VLSI CIRCUITS;

LOGIC SYNTHESIS; ROUTING; WIRE LENGTH;

INTEGRATED CIRCUIT LAYOUT;

EID: 4444224687     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996726     Document Type: Conference Paper

References (26)

1. S.Bodapati and F.N.Najm, "Pre-layout estimation of individual wire lengths", ACM Intl. Workshop on System-Level Interconnect Prediction, pp.93-98, 2000.
2. A.E.Caldwell, A.B.Kahng and I.L.Markov, "Can recursive bisection alone produce routable placements", Design Automation Conference, pp.260-263, 2000.
3. T. F. Chan, J. Cong, J. Shinnerl and K. Sze, "An enhanced multilevel algorithm for circuit placement," Proc. of ICCAD, 2003.
4. C.C.Chang, J.Cong and M.Xie, "Optimality and scalability study of existing placement algorithms", ASP-DAC, pp.621-627, 2003.
5. J.Cong and S.K.Lim, "Edge separability based circuit clustering with application to circuit partitioning", ASP-DAC, pp.429-434, 2000.
6. J.A.Davis, V.K.De, and J.D.Meindl, "A stochastic wire-length distribution for gigascale integration (GSI)-Part I: Derivation and validation", IEEE Trans, on Electron Devices, vol.45, pp.580-589, 1998.
7. S.Hauck and G.Borriello, "An evaluation of bipartitioning techniques", IEEE Trans. on CAD, vol 16, No.8, 1997.
8. B .Hu and M.Marek-Sadowska, "Fine-granularity clustering for large-scale placement problems", Proc. of ISPD, pp.67-74, 2003.
9. B.Hu and M.Marek-Sadowska, "Wire length prediction based clustering and its application in placement", Design Automation Conference, pp.800-805, 2003.
10. V.N.Kravets and P.Kudva, "Understanding metrics in logic synthesis for routability enhancement", ACM Intl. Workshop on System-Level Interconnect Prediction, pp.3-5, 2003.
11. P.Kudva, A.Sullivan and W. Dougherty, "Metrics for structural logic synthesis", Proc. of ICCAD, pp. 551-556, 2002.
12. T.Kutzschebauch and L.Stok, "Congestion aware layout driven logic synthesis", Proc. of ICCAD, pp. 216-223, 2001.
13. Q.Liu, B.Hu and M.Marek-Sadowska, "Wire length prediction in constraint driven placement", ACM Intl. Workshop on System-Level Interconnect Prediction, pp.99-105, 2003.
14. J.Lou, W.Chen and M.Pedram, "Concurrent logic restructuring and placement for timing closure", Proc. of ICCAD, pp. 31-35, 1999.
15. J.Lou, S.Krishnamoorthy and H.S.Sheng, "Estimating routing congestion using probabilistic analysis", Proc. of ISPD, pp. 112-117, 2001.
16. M.Murofushi, T.Ishioka, M.Murakata and T.Mitsuhashi, "Layout driven re-synthesis for low power consumption LSIs", Design Automation Conference, pp. 666-669, 1997.
17. D.Pandini, L.T.Pileggi and A.J.Strojwas, "Congestion aware logic synthesis", Proc. of DATE, pp. 664-671, 2002.
18. M.Pedram and N.Bhat, "Layout driven technology mapping", Design Automation Conference, pp.99-105, 1991.
19. M.Pedram and B.Preas, "Accurate prediction of physical design characteristics for random logic", Proc. of Int. Conf. on Computer Design, pp.390-393, Nov. 1989.
20. D.Stroobandt and J.Van Campenhout, "Accurate interconnection length estimations for predictions early in the design cycle", VLSI Design, vol. 10, no. 1, pp.1-20, 1999.
21. D.Stroobandt, P.Verplaetse and J.Van Campenhout, "Generating synthetic benchmark circuits for evaluating CAD tools", IEEE Trans. on CAD, vol.19, no.9, pp.1011-1022, 2000.
22. H.Vaishnav and M.Pedram, "Minimizing the routing cost during logic extraction", Design Automation Conference, pp.70-75, 1995.
23. M.Wang, X.Yang and M.Sarrafzadeh, "Dragon2000: Standard-cell placement tool for large industry circuits", Proc. of ICCAD, pp. 260-264, 2000
24. X.Yang, R.Kastner and M.Sarrafzadeh, "Congestion estimation during top-down placement", Proc. of ISPD, pp. 164-169, 2001.
25. VLSI CAD Bookshelf:http://gigascale.org/bookshelf/.
26. LGSynth93 benchmarks: http://www.cbl.ncsu.edu/pub/Benchmark_dirs/LGSynth93/