Boosting: Min-cut placement with improved signal delay

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1098-1103

  Kahng, Andrew B ^a   Markov, Igor L ^b   Reda, Sherief ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b The Department of Civil and Environmental Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MIN-CUT PLACEMENT; ROUTING; SIGNAL DELAYS; MIN-CUT; RUNTIMES; TIMING ANALYSIS; TIMING CLOSURES; TOPDOWN; WIRE LENGTH;

BUFFER STORAGE; DELAY CIRCUITS; FORMAL LOGIC; OPTIMIZATION; SIGNAL PROCESSING; EXHIBITIONS;

VLSI CIRCUITS; PLACERS;

EID: 3042660313     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269039     Document Type: Conference Paper

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