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Volumn , Issue , 2000, Pages 693-698

GTX: The MARCO GSRC technology extrapolation system

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EXPERT SYSTEMS; EXTRAPOLATION; GRAPHICAL USER INTERFACES; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

EID: 0033720599     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855404     Document Type: Article
Times cited : (32)

References (20)
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    • J. Cong D. Z. Pan Interconnect Delay Estimation Models for Synthesis and Design Planning ASP-DAC 97 100 ASP-DAC 1999
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    • Cong, J.1    Pan, D.Z.2
  • 6
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    • A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001
    • J. C. Eble V. K. De D. S. Wills J. D. Meindl A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001 Proc. ASIC Conf. 193 196 Proc. ASIC Conf. 1996
    • (1996) , pp. 193-196
    • Eble, J.C.1    De, V.K.2    Wills, D.S.3    Meindl, J.D.4
  • 7
    • 0032027733 scopus 로고    scopus 로고
    • The Test of Time: Clock-Cycle Estimation and Test Challenges for Future Microprocessors
    • P. D. Fisher R. Nesbitt The Test of Time: Clock-Cycle Estimation and Test Challenges for Future Microprocessors IEEE Circuits and Devices Magazine 14 2 37 44 1998
    • (1998) IEEE Circuits and Devices Magazine , vol.14 , Issue.2 , pp. 37-44
    • Fisher, P.D.1    Nesbitt, R.2
  • 8
    • 85177139612 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors December 1999 Semiconductor Industry Association (SIA) http://www.itrs.net/
    • (1999)
  • 9
    • 84888957363 scopus 로고    scopus 로고
    • Interconnect Tuning Strategies for High-Performance ICs
    • A. B. Kahng S. Muddu E. Sarto R. Sharma Interconnect Tuning Strategies for High-Performance ICs Proc. DATE Proc. DATE 1998
    • (1998)
    • Kahng, A.B.1    Muddu, S.2    Sarto, E.3    Sharma, R.4
  • 10
    • 85177110578 scopus 로고    scopus 로고
    • MARCO GSRC Technology Extrapolation Initiative http://vlsicad.cs.ucla.edu/GSRC/GTX/
  • 11
    • 0029544642 scopus 로고
    • A Scaling Scheme for Interconnect in Deep-Submicron Processes
    • K. Rahmat O. S. Nakagawa S.-Y. Oh J. Moll A Scaling Scheme for Interconnect in Deep-Submicron Processes Intl. Electron Devices Meeting. Technical Digest 245 248 Intl. Electron Devices Meeting. Technical Digest 1995
    • (1995) , pp. 245-248
    • Rahmat, K.1    Nakagawa, O.S.2    Oh, S.-Y.3    Moll, J.4
  • 12
    • 0029250448 scopus 로고
    • A Framework for Insight into the Impact of Interconnect on 0.35-um VLSI Performance
    • P. Raje A Framework for Insight into the Impact of Interconnect on 0.35-um VLSI Performance Hewlett-Packard J. 1 8 1995
    • (1995) Hewlett-Packard J. , pp. 1-8
    • Raje, P.1
  • 13
    • 1942468109 scopus 로고    scopus 로고
    • Design Sheet: A System for Exploring Design Space
    • S. Y. Reddy K. W. Fertig Design Sheet: A System for Exploring Design Space Proc. Artificial Intelligence in Design 347 366 Proc. Artificial Intelligence in Design 1996
    • (1996) , pp. 347-366
    • Reddy, S.Y.1    Fertig, K.W.2
  • 14
    • 85177140315 scopus 로고    scopus 로고
    • Rensselaer Interconnect Performance Estimator (RIPE) http://latte.cie.rpi.edu/ripe.html
  • 15
    • 0029207481 scopus 로고
    • Performance Trends in High-Performance Processors
    • G. A. Sai-Halasz Performance Trends in High-Performance Processors Proc. IEEE 20 36 Jan. 1995
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  • 16
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    • Device and Circuit Design Issues in SOI Technology
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    • (1998) , pp. 339-346
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  • 17
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    • Getting to the Bottom of Deep Submicron
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    • Sylvester, D.1    Keutzer, K.2
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.