Toward the accurate prediction of placement wire length distributions in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 4, 2004, Pages 339-348

  Dambre, Joni ^a   Stroobandt, Dirk ^a   Van Campenhout, Jan ^a  

^a GHENT UNIVERSITY   (Belgium)

Author keywords

Design space exploration; Donath's wire length estimation technique; Interconnect prediction; Placement

Indexed keywords

CONSTRAINT THEORY; ELECTRIC CURRENTS; ELECTRIC WIRE; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NONLINEAR SYSTEMS; PRODUCT DESIGN; TOPOLOGY;

DESIGN SPACE EXPLORATION; DONATH'S WIRE LENGTH ESTIMATION TECHNIQUE; INTERCONNECT PREDICTION; PLACEMENT;

VLSI CIRCUITS;

EID: 2442706907     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.825851     Document Type: Conference Paper

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