Multilevel global placement with congestion control

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 395-409

  Chang, Chin Chih ^a,b   Cong, Jason ^a   Pan, Zhigang ^c   Yuan, Xin ^a  

^a University of California   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Congestion; Deep submicrometer; Interconnect; Physical hierarchy; Placement; Routing

Indexed keywords

ALGORITHMS; ESTIMATION; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; OPTIMIZATION; TREES (MATHEMATICS);

HIERARCHICAL AREA DENSITY CONTROL; MULTILEVEL GLOBAL PLACEMENT ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037387778     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809661     Document Type: Article

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