Partitioning multi-threaded processors with a large number of threads

ISPASS 2005 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn 2005, Issue , 2005, Pages 112-123

  El Moursy, Ali ^a   Garg, Rajeev ^a   Albonesi, David H ^b   Dwarkadas, Sandhya ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

^b Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLUSTERED MULTI-THREADED (CMT) PROCESSOR; DESIGN COMPLEXITY; MONOLITHIC HARDWARE; POWER DISSIPATION; QUEUE STRUCTURES; SIMULTANEOUS MULTI-THREADING (SMT);

COMPUTER AIDED DESIGN; COMPUTER HARDWARE; MICROPROCESSOR CHIPS; QUEUEING NETWORKS;

PROGRAM PROCESSORS;

EID: 33744482582     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2005.1430566     Document Type: Conference Paper

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