Instruction replication for clustered microarchitectures

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 326-335

  Aleta A ^a   Codina, J M ^a   Gonzalez A ^a   Kaeli, D ^b  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b NORTHEASTERN UNIVERSITY   (United States)

Author keywords

Computer architecture; Degradation; Delay; Digital signal processing; Microarchitecture; Performance loss; Power dissipation; Processor scheduling; Scheduling algorithm; Wire

Indexed keywords

DEGRADATION; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; ENERGY DISSIPATION; MULTIPROCESSING SYSTEMS; SCHEDULING ALGORITHMS; SIGNAL PROCESSING; WIRE;

CLUSTERED MICROARCHITECTURES; COMPILATION TECHNIQUES; DELAY; INTERCLUSTER COMMUNICATION; MICRO ARCHITECTURES; PERFORMANCE LOSS; PROCESSOR RESOURCES; PROCESSOR SCHEDULING;

COMPUTER ARCHITECTURE;

EID: 84944394490     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253206     Document Type: Conference Paper

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