Clustered approach to multithreaded processors

Proceedings of the International Parallel Processing Symposium, IPPS

Volumn , Issue , 1998, Pages 627-634

  Krishnan, Venkata ^a   Torrellas, Josep ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MULTIPROGRAMMING; PARALLEL PROCESSING SYSTEMS;

SIMULTANEOUS MULTITHREADING (SMT);

MICROPROCESSOR CHIPS;

EID: 0031652125     PISSN: 10637133     EISSN: None     Source Type: None    
DOI: 10.1109/IPPS.1998.669992     Document Type: Conference Paper

References (19)

1. W. Blume R. Doallo R. Eigenmann J. Grout J. Hoeflinger T. Lawrence J. Lee D. Padua Y. Paek B. Pottenger L. Rauchwerger P. Tu Parallel programming with Polaris IEEE Computer 29 12 78 82 December 1996
2. A superscalar Alpha processor with out-of-order execution October 1996 21264
3. P. Dubey K. O'Brien K. O'Brien C. Barton Single-program speculative multithreading (SPSM) architecture: Compiler-assisted fine-grained multithreading Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '95 109 121 Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '95 1995-June
4. M. Franklin G. Sohi ARB: A hardware mechanism for dynamic memory disambiguation IEEE Transactions on Computers 45 5 552 571 May 1996
5. M. Hall J. Anderson S. Amarasinghe B. Murphy S.-W. Liao E. Bugnion M. Lam Maximizing multiprocessor performance with the SUIF compiler IEEE Computer 29 12 84 89 December 1996
6. V. Krishnan J. Torrellas Efficient use of processing transistors for larger on-chip storage: Multithreading Workshop on Mixing Logic and DRAM: Chips that Compute and Remember Workshop on Mixing Logic and DRAM: Chips that Compute and Remember 1997-June
7. V. Krishnan J. Torrellas Executing sequential binaries on a clustered multithreaded architecture with speculation support 4th High Performance Computer Architecture (HPCA) Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98) 4th High Performance Computer Architecture (HPCA) Workshop on Multi-Threaded Execution, Architecture and Compilation (MTEAC'98) 1998-February
8. D. Lenoski J. Laudon K. Gharachorloo A. Gupta J. Hennessy The directory-based cache coherence protocol for the DASH multiprocessor 17th International Symposium on Computer Architecture 148 159 17th International Symposium on Computer Architecture 1990-May
9. J. Lo S. Eggers J. Emer H. Levy R. Stamm D. Tullsen Converting thread-level parallelism into instruction-level parallelism via simultaneous multithreading ACM Transactions on Computer Systems 322 354 August 1997
10. E. Lusk Portable Programs for Parallel Processors 1987 Holt, Rinehart and Winston Inc. New York
11. K. Olukotun B. Nayfeh L. Hammond K. Wilson K. Chang The case for a single-chip multiprocessor 7th International Conference on Architectural Support for Programming Languages and Operating Systems 2 11 7th International Conference on Architectural Support for Programming Languages and Operating Systems 1996-October
12. S. Palacharla N. Jouppi J. Smith Complexity-effective superscalar processors 24th International Symposium on Computer Architecture 206 218 24th International Symposium on Computer Architecture 1997-June
13. E. Rotenberg S. Bennett J. Smith Trace cache: A low latency approach to high bandwidth instruction fetching 29th International Symposium on Microarchitecture 29th International Symposium on Microarchitecture 1996-December
14. G. Sohi S. Breach T. Vijayakumar Multiscalar processors 22nd International Symposium on Computer Architecture 414 425 22nd International Symposium on Computer Architecture 1995-June
15. J. Tsai P. Yew The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '96) 35 46 Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '96) 1996-October
16. D. Tullsen S. Eggers J. Emer H. Levy J. Lo R. Stamm Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor 23rd International Symposium on Computer Architecture 191 202 23rd International Symposium on Computer Architecture 1996-May
17. D. Tullsen S. Eggers H. Levy Simultaneous multithreading: Maximizing on-chip parallelism 22nd International Symposium on Computer Architecture 392 403 22nd International Symposium on Computer Architecture 1995-June
18. J. Veenstra R. Fowler MINT: A front end for efficient simulation of shared-memory multiprocessors Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS'94) 201 207 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS'94) 1994-January
19. S. Woo M. Ohara E. Torrie J. Singh A. Gupta The SPLASH-2 programs: Characterization and methodological considerations 22nd International Symposium on Computer Architecture 24 36 22nd International Symposium on Computer Architecture 1995-June