The simulation of a new asymmetrical double-gate poly-Si TFT with modified channel conduction mechanism for highly reduced OFF-state leakage current

IEEE Transactions on Device and Materials Reliability

Volumn 5, Issue 4, 2005, Pages 675-682

  Orouji, Ali A ^a,b   Jagadesh Kumar, M ^a,c,d  

^a IEEE   (Iran)

^b SEMNAN UNIVERSITY   (Iran)

^c INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^d Institution of Electronics and Telecommunication Engineers IETE   (India)

Author keywords

Double gate; Grain boundary; Leakage current, polysilicon; Pseudosubthreshold; Thin film transistor (TFT); Traps; Two dimensional simulation

Indexed keywords

DOUBLE GATES; GATE-INDUCED GRAIN BARRIER LOWERING (GIGBL); TRAPS; TWO-CARRIER DEVICE SIMULATION;

GATES (TRANSISTOR); LEAKAGE CURRENTS; MODULATION; THIN FILM TRANSISTORS;

POLYSILICON;

EID: 31044450695     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2005.860558     Document Type: Article

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