Device simulation of grain boundaries in lightly doped polysilicon films and analysis of dependence on defect density

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 40, Issue 1, 2001, Pages 49-53

  Kimura, Mutsumi ^a   Inoue, Satoshi ^a   Shimoda, Tatsuya ^a   Sameshima, Toshiyuki ^b  

^a SEIKO EPSON CORPORATION   (Japan)

^b TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

Author keywords

Defect; Device simulation; Electric conductivity; Grain boundary; Lightly dope; Polysilicon; Potential barrier

Indexed keywords

CARRIER CONCENTRATION; COMPUTER SIMULATION; CRYSTAL DEFECTS; ELECTRIC CONDUCTIVITY OF SOLIDS; ELECTRIC SPACE CHARGE; ELECTRON TRAPS; FERMI LEVEL; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; POLYSILICON; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING;

POTENTIAL BARRIER;

SEMICONDUCTING FILMS;

EID: 0035056539     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.40.49     Document Type: Article

References (13)