Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain

IEEE Transactions on Electron Devices

Volumn 49, Issue 5, 2002, Pages 718-724

  Zhang, Shengdong ^b   Han, Ruqi ^b   Sin, Johnny K O ^a,c   Chan, Mansun ^a,c  

^a IEEE

^b PEKING UNIVERSITY   (China)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Double gate; Self aligned; Thin film transistor

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COMPUTER SIMULATION; CRYSTALLIZATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC FIELDS; GATES (TRANSISTOR); GRAIN SIZE AND SHAPE; INTEGRATED CIRCUIT MANUFACTURE; PERFORMANCE; POLYSILICON; SEMICONDUCTOR DEVICE STRUCTURES;

METAL INDUCED UNILATERAL CRYSTALLIZATION; SACRIFICIAL LAYER REPLACEMENT; SELF ALIGNED DOUBLE GATE THIN FILM TRANSISTOR; THICK SOURCE-DRAIN REGION;

THIN FILM TRANSISTORS;

EID: 0036565151     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.998576     Document Type: Article

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