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Volumn 52, Issue 8, 2005, Pages 1815-1820

A new poly-Si TG-TFT with diminished pseudosubthreshold region: Theoretical investigation and analysis

Author keywords

Grain boundary; Leakage current; Polysilicon; Pseudosubthreshold; Thin film transistor (TFT); Traps; Two dimensional (2 D) simulation

Indexed keywords

COMPUTER SIMULATION; ELECTRON TRAPS; GATES (TRANSISTOR); GRAIN BOUNDARIES; LEAKAGE CURRENTS; POLYSILICON; SEMICONDUCTOR DEVICE MODELS; THRESHOLD VOLTAGE;

EID: 23344449825     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.852169     Document Type: Article
Times cited : (13)

References (31)
  • 1
    • 0027839373 scopus 로고
    • "An LCD addressed by a-Si: H TFTs with peripheral poly-Si TFT circuits"
    • T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, and N. Konishi, "An LCD addressed by a-Si: H TFTs with peripheral poly-Si TFT circuits," in IEDM Tech. Dig., 1993, pp. 389-392.
    • (1993) IEDM Tech. Dig. , pp. 389-392
    • Tanaka, T.1    Asuma, H.2    Ogawa, K.3    Shinagawa, Y.4    Konishi, N.5
  • 2
    • 0030150105 scopus 로고    scopus 로고
    • "Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels with peripheral driver circuit integration"
    • May
    • T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, "Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels with peripheral driver circuit integration," IEEE Trans. Electron Devices, vol. 43, no. 5, pp. 701-705, May 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.5 , pp. 701-705
    • Aoyama, T.1    Ogawa, K.2    Mochizuki, Y.3    Konishi, N.4
  • 5
    • 0029246215 scopus 로고
    • "High performance poly-Si TFT fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing"
    • Feb.
    • A. Kohno, T. Sameshima, N. Sano, M. Sekiya, and M. Hara, "High performance poly-Si TFT fabricated using pulsed laser annealing and remote plasma CVD with low temperature processing," IEEE Trans. Electron Devices, vol. 42, no. 2, pp. 251-257, Feb. 1995.
    • (1995) IEEE Trans. Electron Devices , vol.42 , Issue.2 , pp. 251-257
    • Kohno, A.1    Sameshima, T.2    Sano, N.3    Sekiya, M.4    Hara, M.5
  • 6
    • 0026818616 scopus 로고
    • "Conduction mechanism of leakage current observed in metal-oxide-semiconductor transistors and poly-Si thin-film transistors"
    • M. Yazaki, S. Takenaka, and H. Oshima, "Conduction mechanism of leakage current observed in metal-oxide-semiconductor transistors and poly-Si thin-film transistors," Jpn. J. Appl. Phys., vol. 31, pp. 206-209, 1992.
    • (1992) Jpn. J. Appl. Phys. , vol.31 , pp. 206-209
    • Yazaki, M.1    Takenaka, S.2    Oshima, H.3
  • 7
    • 0030384711 scopus 로고    scopus 로고
    • "A novel polysilicon thin-film transistor with a p-n-p structured gate electrode"
    • Dec.
    • B. Min, C. Park, and M. Han, "A novel polysilicon thin-film transistor with a p-n-p structured gate electrode," IEEE Electron Device Lett., vol. 17, no. 12, pp. 560-562, Dec. 1996.
    • (1996) IEEE Electron Device Lett. , vol.17 , Issue.12 , pp. 560-562
    • Min, B.1    Park, C.2    Han, M.3
  • 8
    • 4043137371 scopus 로고    scopus 로고
    • "Characteristics of high-κ spacer offset-gated polysilicon TFTs"
    • Aug.
    • Z. Xiong, H. Liu, C. Zhu, and J. K.O. Sin, "Characteristics of high-κ spacer offset-gated polysilicon TFTs," IEEE Trans. Electron Devices, vol. 51, no. 8, pp. 1304-1308, Aug. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.8 , pp. 1304-1308
    • Xiong, Z.1    Liu, H.2    Zhu, C.3    Sin, J.K.O.4
  • 9
    • 0442295642 scopus 로고    scopus 로고
    • "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel"
    • Feb.
    • P. M. Walker, H. Mizuta, S. Uno, Y. Futura, and D. G. Hasko, "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 212-219, Feb. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.2 , pp. 212-219
    • Walker, P.M.1    Mizuta, H.2    Uno, S.3    Futura, Y.4    Hasko, D.G.5
  • 11
    • 0035447817 scopus 로고    scopus 로고
    • "A new polycrystalline silicon TFT with a single grain boundary in the channel"
    • Sep.
    • J.-H. Jeon, M.-C. Lee, K.-C. Park, and M.-K. Han, "A new polycrystalline silicon TFT with a single grain boundary in the channel," IEEE Electron Device Lett., vol. 22, no. 9, pp. 429-431, Sep. 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , Issue.9 , pp. 429-431
    • Jeon, J.-H.1    Lee, M.-C.2    Park, K.-C.3    Han, M.-K.4
  • 12
    • 0035120897 scopus 로고    scopus 로고
    • "A proposed single-boundary thin-film transistor"
    • Jan.
    • C.-H. Oh and M. Matsumura, "A proposed single-boundary thin-film transistor," IEEE Electron Device Lett., vol. 22, no. 1, pp. 20-22, Jan. 2001.
    • (2001) IEEE Electron Device Lett. , vol.22 , Issue.1 , pp. 20-22
    • Oh, C.-H.1    Matsumura, M.2
  • 13
    • 0003690029 scopus 로고    scopus 로고
    • "High performance low-temperature processes polysilicon TFTs fabricated by excimer laser crystallization with recessed-channel structure"
    • H.-C. Cheng, L.-J. Cheng, C.-W. Lin, Y.-L. Lu, and C.-Y. Chen, "High performance low-temperature processes polysilicon TFTs fabricated by excimer laser crystallization with recessed-channel structure," in AMLCD Tech. Dig., 2000, p. 281.
    • (2000) AMLCD Tech. Dig. , pp. 281
    • Cheng, H.-C.1    Cheng, L.-J.2    Lin, C.-W.3    Lu, Y.-L.4    Chen, C.-Y.5
  • 15
    • 0032137394 scopus 로고    scopus 로고
    • "Low-temperature single-crystal Si TFTs fabricated on Si films processed via sequential lateral solidification"
    • Apr.
    • M. A. Crowder, P. G. Carey, P. M. Smith, R. S. Sposili, H. S. Cho, and J. S. Im, "Low-temperature single-crystal Si TFTs fabricated on Si films processed via sequential lateral solidification," IEEE Electron Device Lett., vol. 19, no. 4, pp. 306-308, Apr. 1998.
    • (1998) IEEE Electron Device Lett. , vol.19 , Issue.4 , pp. 306-308
    • Crowder, M.A.1    Carey, P.G.2    Smith, P.M.3    Sposili, R.S.4    Cho, H.S.5    Im, J.S.6
  • 17
    • 0027592564 scopus 로고
    • "On the pseudosubthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size"
    • May
    • T.-S. Li and P.-S. Lin, "On the pseudosubthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size," IEEE. Electron Device Lett., vol. 14, no. 5, pp. 240-242, May 1993.
    • (1993) IEEE. Electron Device Lett. , vol.14 , Issue.5 , pp. 240-242
    • Li, T.-S.1    Lin, P.-S.2
  • 18
    • 0030241288 scopus 로고    scopus 로고
    • "Threshold voltage, field effect mobility, and gate-to channel capacitance in polysilicon TFTs"
    • Sep.
    • M. D. Jacunski, M. S. Shur, and M. Hack, "Threshold voltage, field effect mobility, and gate-to channel capacitance in polysilicon TFTs," IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1433-1440, Sep. 1996.
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.9 , pp. 1433-1440
    • Jacunski, M.D.1    Shur, M.S.2    Hack, M.3
  • 19
    • 11744261148 scopus 로고    scopus 로고
    • Palo Alto, CA: Technology Modeling Associates
    • MEDICI 4.0 User's Manual. Palo Alto, CA: Technology Modeling Associates, 1997.
    • (1997) MEDICI 4.0 User's Manual
  • 20
    • 0009509593 scopus 로고
    • "Carrier mobilities in silicon empirically related to doping and field"
    • D. M. Caughey and R. E. Thomas, "Carrier mobilities in silicon empirically related to doping and field," Proc. IEEE, vol. 55, pp. 2192-2193, 1967.
    • (1967) Proc. IEEE , vol.55 , pp. 2192-2193
    • Caughey, D.M.1    Thomas, R.E.2
  • 21
    • 0346935141 scopus 로고    scopus 로고
    • "Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors"
    • Dec.
    • Y. Kitahara, S. Takagi, and N. Sano, "Statistical study of subthreshold characteristics in polycrystalline silicon thin-film transistors," J. Appl. Phys., vol. 94, pp. 7789-7795, Dec. 2003.
    • (2003) J. Appl. Phys. , vol.94 , pp. 7789-7795
    • Kitahara, Y.1    Takagi, S.2    Sano, N.3
  • 22
    • 0346935143 scopus 로고    scopus 로고
    • "Modeling and simulation of polycrystalline Zno thin-film transistors"
    • Dec.
    • F. M. Hossain, J. Nishii, S. Takagi, A. Ohtomo, and T. Fukumura, "Modeling and simulation of polycrystalline Zno thin-film transistors," J. Appl. Phys., vol. 94, pp. 7768-7777, Dec. 2003.
    • (2003) J. Appl. Phys. , vol.94 , pp. 7768-7777
    • Hossain, F.M.1    Nishii, J.2    Takagi, S.3    Ohtomo, A.4    Fukumura, T.5
  • 23
    • 5344267571 scopus 로고
    • "Pixel design of TFT-LCDs for high quality images"
    • K. Suzuki, "Pixel design of TFT-LCDs for high quality images," in Proc. SID Symp., 1992, pp. 39-42.
    • (1992) Proc. SID Symp. , pp. 39-42
    • Suzuki, K.1
  • 24
    • 0016597193 scopus 로고
    • "The electrical properties of polycrystalline silicon films"
    • Dec.
    • J. Y. W. Seto, "The electrical properties of polycrystalline silicon films," J. Appl. Phys., vol. 46, pp. 5247-5254, Dec. 1975.
    • (1975) J. Appl. Phys. , vol.46 , pp. 5247-5254
    • Seto, J.Y.W.1
  • 25
    • 0018032498 scopus 로고
    • "Transport properties of polycrystalline silicon films"
    • Nov
    • G. Baccarani, B. Ricco, and G. Spadini, "Transport properties of polycrystalline silicon films," J. Appl. Phys., vol. 49, pp. 5565-5570, Nov. 1978.
    • (1978) J. Appl. Phys. , vol.49 , pp. 5565-5570
    • Baccarani, G.1    Ricco, B.2    Spadini, G.3
  • 26
    • 0035056539 scopus 로고    scopus 로고
    • "Device simulation of grain boundaries in lightly doped polysilicon films and analysis of dependence on defect density"
    • Jan.
    • M. Kimura, S. Inoue, T. Shimoda, and T. Sameshima, "Device simulation of grain boundaries in lightly doped polysilicon films and analysis of dependence on defect density," Jpn. J. Appl. Phys., vol. 40, pp. 49-53, Jan. 2001.
    • (2001) Jpn. J. Appl. Phys. , vol.40 , pp. 49-53
    • Kimura, M.1    Inoue, S.2    Shimoda, T.3    Sameshima, T.4
  • 27
    • 0020089602 scopus 로고
    • "Conductivity behavior in polycrystalline semiconductor thin film transistors"
    • Feb.
    • J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, pp. 1193-1202, Feb. 1982.
    • (1982) J. Appl. Phys. , vol.53 , pp. 1193-1202
    • Levinson, J.1    Shepherd, F.R.2    Scanlon, P.J.3    Westwood, W.D.4    Este, G.5    Rider, M.6
  • 28
    • 1942423745 scopus 로고    scopus 로고
    • "Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs"
    • Apr.
    • M. J. Kumar and A. Chaudhry, "Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs," IEEE Trans. Electron Devices, vol. 51, no. 4, pp. 569-574, Apr. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.4 , pp. 569-574
    • Kumar, M.J.1    Chaudhry, A.2
  • 29
    • 4444274252 scopus 로고    scopus 로고
    • "Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET"
    • Sep.
    • A. Chaudhry and M. J. Kumar, "Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1463-1467, Sep. 2004.
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.9 , pp. 1463-1467
    • Chaudhry, A.1    Kumar, M.J.2
  • 30
    • 2342583496 scopus 로고    scopus 로고
    • "Controlling short-channel effects in deep submicron SOI MOSFETs for improved reliability: A review"
    • Mar.
    • A. Chaudhry and M. J. Kumar, "Controlling short-channel effects in deep submicron SOI MOSFETs for improved reliability: A review," IEEE Trans. Device Mater. Reliab., vol. 4, no. 3, pp. 99-109, Mar. 2004.
    • (2004) IEEE Trans. Device Mater. Reliab. , vol.4 , Issue.3 , pp. 99-109
    • Chaudhry, A.1    Kumar, M.J.2
  • 31
    • 15844418329 scopus 로고    scopus 로고
    • "A new dual-material double-gate (DMDG) nanoscale SOI MOSFET - Two-dimensional analytical modeling and simulation"
    • Mar.
    • G. V. Reddy and M. J. Kumar, "A new dual-material double-gate (DMDG) nanoscale SOI MOSFET - Two-dimensional analytical modeling and simulation," IEEE Trans. Nanotechnol., vol. 4, no. 3, pp. 260-268, Mar. 2005.
    • (2005) IEEE Trans. Nanotechnol. , vol.4 , Issue.3 , pp. 260-268
    • Reddy, G.V.1    Kumar, M.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.