-
2
-
-
0031359423
-
The on-resistance limits of high cell density power MOSFET's
-
Morancho F, Tranduc H, Rossel P. The on-resistance limits of high cell density power MOSFET's. In: Proc MIEL, 1997. p. 395-8
-
(1997)
Proc MIEL
, pp. 395-398
-
-
Morancho, F.1
Tranduc, H.2
Rossel, P.3
-
3
-
-
0041438345
-
30 V new fine trench MOSFET with ultra low on-resistance
-
Ono S, Kawaguchi Y, Nakagawa A. 30 V new fine trench MOSFET with ultra low on-resistance. In: Proc ISPSD, 2003. p. 28-31
-
(2003)
Proc ISPSD
, pp. 28-31
-
-
Ono, S.1
Kawaguchi, Y.2
Nakagawa, A.3
-
4
-
-
0041438343
-
A new power W-gated trench MOSFET (WMOSFET) with high switching performance
-
Darwish M, Yue C, Lui KH, Giles F, Chan B, Chen KI, et al. A new power W-gated trench MOSFET (WMOSFET) with high switching performance. In: Proc ISPSD, 2003. p. 24-7
-
(2003)
Proc ISPSD
, pp. 24-27
-
-
Darwish, M.1
Yue, C.2
Lui, K.H.3
Giles, F.4
Chan, B.5
Chen, K.I.6
-
5
-
-
3943065749
-
Gate-drain charge analysis for switching in power trench MOSFETs
-
R.J.E. Hueting, E.A. Hijzen, A. Heringa, A.W. Ludikhuize, and M.A.A. in'tZandt Gate-drain charge analysis for switching in power trench MOSFETs IEEE Trans Electron Dev 51 8 2004 1323 1330
-
(2004)
IEEE Trans Electron Dev
, vol.51
, Issue.8
, pp. 1323-1330
-
-
Hueting, R.J.E.1
Hijzen, E.A.2
Heringa, A.3
Ludikhuize, A.W.4
In'tZandt, M.A.A.5
-
6
-
-
0042440615
-
Novel process techniques for fabricating high density trench MOSFETs with self-aligned N+/P+ source formed on the trench side wall
-
Park IY, Kim SG, Koo JG, Kim J. Novel process techniques for fabricating high density trench MOSFETs with self-aligned N+/P+ source formed on the trench side wall. In: Proc ISPSD, 2003. p. 169-72
-
(2003)
Proc ISPSD
, pp. 169-172
-
-
Park, I.Y.1
Kim, S.G.2
Koo, J.G.3
Kim, J.4
-
7
-
-
0042164626
-
Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation
-
V.D. Kunz, T. Uchino, C.H. de Groot, P. Ashburn, D.C. Donaghy, and S. Hall Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation IEEE Trans Electron Dev 50 6 2003 1487 1493
-
(2003)
IEEE Trans Electron Dev
, vol.50
, Issue.6
, pp. 1487-1493
-
-
Kunz, V.D.1
Uchino, T.2
De Groot, C.H.3
Ashburn, P.4
Donaghy, D.C.5
Hall, S.6
-
8
-
-
0029717332
-
Vertical, fully depleted, surrounding gate MOSFETs on sub-0.1 μm thick silicon pillars
-
Auth CP, Plummer JD. Vertical, fully depleted, surrounding gate MOSFETs on sub-0.1 μm thick silicon pillars. In: Proc Device Research Conference, 1996. p. 108-9
-
(1996)
Proc Device Research Conference
, pp. 108-109
-
-
Auth, C.P.1
Plummer, J.D.2
-
9
-
-
0029209413
-
Moderate inversion model of ultrathin double-gate nMOS/SOI transistors
-
P. Francis, A. Terao, D. Flandre, and F. Van de Wiele Moderate inversion model of ultrathin double-gate nMOS/SOI transistors Solid-State Electron 38 1 1995 171 176
-
(1995)
Solid-State Electron
, vol.38
, Issue.1
, pp. 171-176
-
-
Francis, P.1
Terao, A.2
Flandre, D.3
Van De Wiele, F.4
-
10
-
-
18844435456
-
Reliability study of CMOS FinFETs
-
Yang-Kyu C, Daewon H, Snow E, Bokor J, Tsu-Jae K. Reliability study of CMOS FinFETs. In: Proc IEDM, 2003. p. 761-4
-
(2003)
Proc IEDM
, pp. 761-764
-
-
Yang-Kyu, C.1
Daewon, H.2
Snow, E.3
Bokor, J.4
Tsu-Jae, K.5
-
11
-
-
0035003546
-
The impact of trench geometry and processing on the performance and reliability of low voltage power UMOSFETs
-
Suliman SA, Gallogunta N, Trabzon L, Hao J, Dolny G, Ridley R, et al. The impact of trench geometry and processing on the performance and reliability of low voltage power UMOSFETs. In: Proc Reliability Physics Symposium, 2001. p. 308-14
-
(2001)
Proc Reliability Physics Symposium
, pp. 308-314
-
-
Suliman, S.A.1
Gallogunta, N.2
Trabzon, L.3
Hao, J.4
Dolny, G.5
Ridley, R.6
-
12
-
-
0036867981
-
Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping
-
X. Chen, Q.C. Ouyang, G. Wang, and S.K. Banerjee Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping IEEE Trans Electron Dev 49 11 2002 1962 1967
-
(2002)
IEEE Trans Electron Dev
, vol.49
, Issue.11
, pp. 1962-1967
-
-
Chen, X.1
Ouyang, Q.C.2
Wang, G.3
Banerjee, S.K.4
-
13
-
-
18844456919
-
-
Integr Syst Eng, Inc, San Jose, CA 95113
-
ISE 7.0 USER Manual, Integr Syst Eng, Inc, San Jose, CA 95113, 2001
-
(2001)
ISE 7.0 USER Manual
-
-
-
14
-
-
0031176038
-
The behaviour of very high current density power MOSFET's
-
J. Evans, and G. Amaratunga The behaviour of very high current density power MOSFET's IEEE Trans Electron Dev 44 7 1997 1148 1153
-
(1997)
IEEE Trans Electron Dev
, vol.44
, Issue.7
, pp. 1148-1153
-
-
Evans, J.1
Amaratunga, G.2
-
16
-
-
0021787429
-
A new vertical power MOSFET structure with extremely reduced on-resistance
-
D. Ueda, H. Takagi, and G. Kano A new vertical power MOSFET structure with extremely reduced on-resistance IEEE Trans Electron Dev 32 1 1985 2 6
-
(1985)
IEEE Trans Electron Dev
, vol.32
, Issue.1
, pp. 2-6
-
-
Ueda, D.1
Takagi, H.2
Kano, G.3
-
17
-
-
1542678788
-
Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length
-
F. Allibert, J. Pretet, G. Pananakakis, and S. Cristoloveanu Transition from partial to full depletion in silicon-on-insulator transistors: impact of channel length Appl Phys Lett 84 7 2004 1192 1194
-
(2004)
Appl Phys Lett
, vol.84
, Issue.7
, pp. 1192-1194
-
-
Allibert, F.1
Pretet, J.2
Pananakakis, G.3
Cristoloveanu, S.4
-
18
-
-
4944266275
-
Trench gate power MOSFETs with retrograde body profile
-
Tsui BY, Wu MD, Gan TC, Chou HH, Wu ZL, Sune CT. Trench gate power MOSFETs with retrograde body profile. In: Proc ISPSD, 2004. p. 213-6
-
(2004)
Proc ISPSD
, pp. 213-216
-
-
Tsui, B.Y.1
Wu, M.D.2
Gan, T.C.3
Chou, H.H.4
Wu, Z.L.5
Sune, C.T.6
-
19
-
-
0742320771
-
Optimum design for minimum on-resistance of low voltage trench power MOSFET
-
J.H. Hong, S.K. Chung, and Y.I. Choi Optimum design for minimum on-resistance of low voltage trench power MOSFET Microelectr J. 35 3 2004 287 289
-
(2004)
Microelectr J.
, vol.35
, Issue.3
, pp. 287-289
-
-
Hong, J.H.1
Chung, S.K.2
Choi, Y.I.3
-
22
-
-
0030397256
-
A closed form solution of junction to substrate thermal resistance in semiconductor chips
-
F.N. Masana A closed form solution of junction to substrate thermal resistance in semiconductor chips IEEE Trans Components, Hybrids, and Manufacturing Technology 19 4 1996 539 545
-
(1996)
IEEE Trans Components, Hybrids, and Manufacturing Technology
, vol.19
, Issue.4
, pp. 539-545
-
-
Masana, F.N.1
-
23
-
-
0030082894
-
Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate
-
J. Zeng, P.A. Mawby, M.S. Towers, and K. Board Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate IEE Proc-Circ Dev Syst 143 1 1996 28 32
-
(1996)
IEE Proc-Circ Dev Syst
, vol.143
, Issue.1
, pp. 28-32
-
-
Zeng, J.1
Mawby, P.A.2
Towers, M.S.3
Board, K.4
-
25
-
-
1442336332
-
Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs
-
M. Chan, P. Su, H. Wan, C.-H. Lin, S.K.-H. Fung, and A.M. Niknejad Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs Solid-State Electron 48 6 2004 969 978
-
(2004)
Solid-State Electron
, vol.48
, Issue.6
, pp. 969-978
-
-
Chan, M.1
Su, P.2
Wan, H.3
Lin, C.-H.4
Fung, S.K.-H.5
Niknejad, A.M.6
-
26
-
-
0032132249
-
Modeling of non-uniform heat dissipation and prediction of hot spots in power transistors
-
L. Zhu, K. Vafai, and L. Xu Modeling of non-uniform heat dissipation and prediction of hot spots in power transistors Int J Heat Mass Transfer 41 15 1998 2399 2407
-
(1998)
Int J Heat Mass Transfer
, vol.41
, Issue.15
, pp. 2399-2407
-
-
Zhu, L.1
Vafai, K.2
Xu, L.3
-
27
-
-
9544244783
-
Modelling of non-uniform heat generation in LDMOS transistors
-
J. Roig, D. Flores, J. Urresti, S. Hidalgo, and J. Rebollo Modelling of non-uniform heat generation in LDMOS transistors Solid-State Electron 49 1 2005 77 84
-
(2005)
Solid-State Electron
, vol.49
, Issue.1
, pp. 77-84
-
-
Roig, J.1
Flores, D.2
Urresti, J.3
Hidalgo, S.4
Rebollo, J.5
-
28
-
-
0030784335
-
Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI
-
Y.K. Leung, S.C. Kuehne, V.S.K. Huang, C.T. Nguyen, and A.K. Paul Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI IEEE Electron Dev Lett 18 1 1997 13 15
-
(1997)
IEEE Electron Dev Lett
, vol.18
, Issue.1
, pp. 13-15
-
-
Leung, Y.K.1
Kuehne, S.C.2
Huang, V.S.K.3
Nguyen, C.T.4
Paul, A.K.5
-
29
-
-
1942487830
-
Hot-carrier degradation phenomena in lateral and vertical DMOS transistors
-
P. Moens, G. Van den bosh, and G. Groeseneker Hot-carrier degradation phenomena in lateral and vertical DMOS transistors IEEE Trans Electron Dev 51 4 2004 623 628
-
(2004)
IEEE Trans Electron Dev
, vol.51
, Issue.4
, pp. 623-628
-
-
Moens, P.1
Van Den Bosh, G.2
Groeseneker, G.3
-
30
-
-
0042164630
-
MOSFET degradation kinetics and its simulation
-
O. Penzin, A. Haggag, W. McMahon, E. Lyumkis, and K. Hess MOSFET degradation kinetics and its simulation IEEE Trans Electron Dev 50 6 2003 1445 1450
-
(2003)
IEEE Trans Electron Dev
, vol.50
, Issue.6
, pp. 1445-1450
-
-
Penzin, O.1
Haggag, A.2
McMahon, W.3
Lyumkis, E.4
Hess, K.5
|